Architectural Bias: a Novel Statistical Metric to Evaluate Arbiter PUF Variants

This paper introduces the notion of Architectural Bias, which can be used to measure the influence of the architecture of Arbiter Physically Unclonable Functions (APUFs) on the quality of its outputs. A PUF design with less architectural bias is better than one which has more architectural bias. Architectural bias is the bias in the challenge-response behavior of a PUF due to the architectural features of the design itself, independent of the implementation platform, technology node and external factors. This bias is different from the bias observed in the APUF outputs when implemented on Field Programmable Gate Array (FPGA) platform. This platform induced bias is called as Implementation Bias. To overcome the effect of implementation bias in classic APUF, Programmable Delay Line APUF (PAPUF) and Double APUF (DAPUF) have been proposed as alternatives for APUF on FPGA platforms. In this work, we provide a comparative analysis of the architectures of APUF and its two design variants based on the derived linear additive delay models. Subsequently, these designs are evaluated with the architectural bias to quantify the number of good (i.e. usable) PUF instances that it can generate. We also develop a scheme to perform instance-level comparison of a pair of randomly selected PUF instances of two different PUF designs. In addition, we study the impacts of architectural bias on PUF performance metrics namely uniformity, uniqueness and reliability. We validate our theoretical findings with simulation and FPGA-based implementation results. Experimental results reveal that the classic APUF has the least architectural bias, followed by the DAPUF and the PAPUF, respectively.